1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and more particularly to a semiconductor memory device and a method of operation thereof.
2. Description of the Related Art
In general, a semiconductor memory device, such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) includes multiple memory banks having a large number of memory cells for storing data Each memory cell may typically include a cell capacitor and a cell transistor. Data are stored by charging or discharging the cell capacitors in the memory cells. The cell transistors function as gates that may permit reading or writing when they are open or simply storing data when they are closed. Ideally an electric charge stored in a cell capacitor should remain constant until it is changed by discharging it, however, in reality the stored charge may change overtime. For example, a charge stored in a cell capacitor may leak away or a discharged cell capacitor may inadvertently gain a charge. Since a charge in each cell capacitor represents one bit of data, a change in the charge may result in loss of data. In order to prevent stored data from being lost, semiconductor memory devices perform a background maintenance operation known as a refresh operation at regular time intervals. Refresh operations are widely known to those skilled in the art, and consist basically of reading and restoring the charge on each capacitor to its original level repeatedly in a consecutive cycle.
A refresh cycle depends upon the time that a charge can remain stored in a memory cell. Hence, if data can remain stored in a memory cell for a long time, it is possible then to reduce the frequency of refresh operations i.e. repeat refresh operations at longer time intervals. If data can be stored in a memory cell only for a short period of time then the refresh cycle should be shorter to prevent loss of data. A semiconductor memory device that can store data for a long period of time without a refresh operation is said to have a good refresh characteristic, while a semiconductor memory device keeping stored data for a short period of time without a refresh operation is said to have a bad refresh characteristic. Improving the refresh characteristic of a semiconductor device is generally desirable because it may also improve the operational efficiency of the semiconductor memory device as the frequency of refresh operations may be reduced.
Generally, there may be various ways to improve the refresh characteristic of semiconductor memory devices. For during the fabrication process of semiconductor memory devices, improvements may be obtained by better control of the making of the cell transistors and capacitors of the memory cells as well as the making of any peripheral circuits coupled to the memory cells. The refresh characteristic may also be improved by controlling the design and operation of each memory cell and the refresh operation related circuits. Fundamentally, since a refresh operation is needed because of electric charges leaking to or from a memory cell, reducing such leakage current should improve the refresh characteristic of a semiconductor memory device.